This invention relates to integrated electronic circuits which require a reference voltage for their operation, and more particularly to means for providing a selectable reference voltage for those circuits. One particular example of such a circuit and a prior art means for providing the reference voltage is illustrated in FIG. 1a. In that figure, the circuit is indicated by reference numeral 10, and the reference voltage generating means is indicated by reference numeral 20.
That particular circuit is a balanced differential amplifier. It consists of a total of seven field effect transistors 11-17 which are interconnected as illustrated. Basically, the function of circuit 10 is to receive a T.sup.2 L input voltage V.sub.I, and to generate an output voltage V.sub.O which indicates whether the input voltage V.sub.I is a logical "1" or a logical "0".
In operation, transistors 11 and 12 are simultaneously turned-on by a clocking singal .phi..sub.1. This turn-on charges the source of those transistors to approximately plus five volts. Subsequently, transistors 11 and 12 are turned-off, and transistor 17 is turned-on by a clocking signal .phi..sub.2. If signal V.sub.I is more positive than the reference voltage V.sub.R, then transistor 16 conducts more than transistor 15. This causes the five volts which was stored at the source of transistor 12 to discharge through transistors 14, 16, and 17. At the same time, transistor 13 turns-off which leaves the voltage at the source of transistor 11 at or near five volts.
Conversely, if the input voltage V.sub.I is less positive than the reference voltage V.sub.R, then the operation of circuit 10 is just the opposite. That is, the voltage at the source of transistor 11 is discharged through transistors 13, 15, and 17; while the voltage at the source of transistor 12 remains at or near five volts. This symmetry of operation is due to the fact that circuit 10 is balanced (i.e., transistors 13 and 14 have identical geometries, and transistors 15 and 16 also have identical geometries).
Such symmetry in circuit 10 is highly desirable because it makes the circuit's operation insensitive to tolerances in the fabrication process. For example, if the nominal widths of transistors 13 and 14 are identical, but they both increase uniformly due to various processing tolerances, then the corresponding electrical parameters in transistors 13 and 14 will also be modified identically and their effects will cancel. This will not be the case if circuit 10 is unbalanced (i.e., if the nominal widths of transistors 13 and 14 were not identical).
However, balanced amplifiers always require a reference voltage which is intermediate between the logical "1" and logical "0" voltage levels of the input voltage V.sub.I that is being sensed. This voltage must be precisely generated. Otherwise, if the reference voltage is too low, then some of the input voltages which actually are a logical "0" will be incorrectly interpreted as a logical "1"; or if the reference voltage is generated too high, then some of the input voltages which actually are a logical "1" will be incorrectly interpreted as a logical "0".
Reference voltage generator 20 of the prior art merely consists of a pair of resistors 21 and 22. These resistors may be fabricated on a semiconductor chip as a patterned diffusion in the substrate, or as a patterned polysilicon layer above the substrate. Both of these types of resistors are unattractive however because they require too large of an area for their implementation. Typically, polysilicon resistors provide only 60 ohms per square, and diffusion resistors provide only 20 ohms per square. Thus, a 50 K ohm resistor requires an area of approximately 1,000 squares for its implementation.
A resistance of less than 50 K ohms would of course occupy less space. But smaller resistors also draw more current and consume more power which makes them unsuitable on a chip. For example, given a five volt supply and a current limitation of 100 microamps, a resistor of at least 50 K ohms would be required.
Reference voltage generator 20 is also unattractive because the reference voltage V.sub.R is too sensitive to changes in the plus five volt supply. For example, if the supply voltage changes by a plus or minus ten percent, then the reference voltage V.sub.R will also change by plus or minus ten percent. Preferably, reference voltage V.sub.R should not directly track such changes in the supply voltage.
Another prior art reference voltage generating circuit is illustrated in FIG. 1b. That circuit consists of a pair of unsymmetrical transistors 31 and 32 which are interconnected as illustrated. Transistor 31 has a channel of length L.sub.A and width W.sub.A ; whereas transistor 32 has a channel of length L.sub.B and width W.sub.B. These dimensional parameters are selectively chosen to obtain the desired voltage V.sub.R. That is, reference voltage V.sub.R is a function of the quantity ##EQU1##
However, a problem with the FIG. 1b circuit is that reference voltage V.sub.R is too sensitive to variations in the dimensions L.sub.A, L.sub.B, W.sub.A, and W.sub.B. If we assume that each dimensional parameter has a tolerance of plus or minus 2e, then reference voltage V.sub.R is actually a function of ##EQU2## This dependence on dimensional tolerances can be reduced by setting W.sub.A equal to W.sub.B ; but even under those conditions, the sensitivity of reference voltage V.sub.R is still too high, as it is a function of ##EQU3##
Having V.sub.R independent of dimensional tolerances is highly desirable because those tolerances are caused by many processing factors. For example, mask tolerances, resist exposure time tolerances, undercutting tolerances of etchants, and energy level tolerances of dopant atoms each give rise to dimensional tolerances. Thus, practically all of the many steps of a fabrication process for a semiconductor device must be tightly controlled in order to eliminate dimensional tolerances and the corresponding variation in reference voltage V.sub.R from the FIG. 1b reference voltage generator.
Still another prior art reference voltage generator is illustrated in FIG. 1c. It consists of a first plurality of serially interconnected transistors 42-1 through 42-M. All of these transistors are identical. That is, they all have identical channel lengths and identical channel widths. Due to this symmetry, reference voltage V.sub.R is insensitive to dimensional tolerances, and is merely a function of the ratio of the number N of transistors in the first plurality divided by the total number of transistors N+M.
One problem however with the FIG. 1c reference voltage generator is that reference voltage V.sub.R is quantized in increments of (1/N+M). Thus, a large number of transistors is required to obtain any reference voltage precisely. But, this is undesirable because the required chip space is directly proportional to the total number of transistors N+M times their gate length plus the total number of transistors N+M times the spacing between adjacent transistors. Typically, the minimal gate length and the minimal spacing between adjacent transistors are equal to each other. Thus, the latter term significantly adds to the required chip space.
Another problem with the FIG. 1c reference voltage generator is that voltage V.sub.R is sensitive to any mask defect which shortens the gate length of one of the transistors beyond the nominal minimal length. For example, if the gate length of transistor 41-2 is so decreased, then that transistor can short and reference voltage V.sub.R will increase by some increment. Conversely, V.sub.R will decrease by some increment if a mask defect causes one of transistors 42-1 through 42-M to short.
Accordingly, it is a primary object of the invention to generating an improved means for generating a reference voltage on a semiconductor chip.
Another object of the invention is to provide a means for generating a reference voltage on a semiconductor chip which occupies a minimal amount of chip space.
Another object of the invention is to provide a means for providing a reference voltage on a semiconductor chip which has minimal sensitivity to dimensional variations.
Another object of the invention is to provide a means for generating a reference voltage on a semiconductor chip which is not quantized.
Another object of the invention is to provide a means for generating a reference voltage on a semiconductor chip which is relatively insensitive to changes in the supply voltage.
Still another object of the invention is to provide a means for generating a reference voltage on a semiconductor chip which is relatively insensitive to mask defects.